07Remembering a Bit

Chapter 6 ended on a confession, and this is the chapter that pays it off. Everything we've built so far shares one trait we never said out loud — every gate, every adder, the whole ALU. It has no past. Its output is a pure function of the inputs sitting on its wires right now. Set the operands and the answer appears. Change them and the old answer is gone without a trace. That property has a name: combinational logic, logic that only ever reacts. It's exactly why a calculator can't remember the number you just computed. So here is the strange question this chapter turns on: how can a machine made entirely of parts with no memory ever remember anything? The answer is almost insultingly small. It's a single wire bent back into a loop. When a gate's output feeds its own input, the machine stops being a function and starts having a history. The same inputs can now give two different outputs, depending on what happened before. That broken determinism isn't a bug. It is memory — the first thing in this whole course that can hold a value on its own. We'll watch an OR gate latch itself to 1 and refuse to let go. We'll build the cross-coupled SR latch that rests in either of two stable states, then gate it so it stores only on command. And we'll finish on the one flaw it can't shake: it listens too much. That flaw is the exact door the clock walks through next chapter. No magic in any of it — just a wire, doing something we've carefully never let a wire do until now.

01When a wire feeds itself

Before we break it, let's be precise about the thing we're breaking, because the whole chapter is a contrast against it. Take any gate we've built — say an AND. Notice its defining virtue: it is a function. Give it the same two inputs a billion times and it hands back the same one bit a billion times. No drift, no history, no "it depends." Its output is decided entirely by the inputs present this instant. That's determinism, and every truth table quietly assumes it — one row per input combination, one fixed answer each. Run a whole tape of chips through the same gate below and watch them all drop the identical colour. There is no yesterday in here.

Now pick the one gate we're about to abuse, and remind yourself exactly how it behaves, because its stubbornness is the whole trick. The OR gate lights its output the instant either input is 1. It goes dark only in the single case where both are 0. Hold that in your head: an OR with even one 1 anywhere on its inputs outputs 1. Flip the two inputs below and confirm it. One lit input is all it takes.

Here's the move we've spent six chapters never making. Take that OR gate and do something that should feel slightly illegal. Run its output wire back around and connect it to one of its own inputs. Now the gate is reading a signal it is itself producing. The same physical wire is both the answer and part of the question. Every circuit until now flowed strictly left-to-right, inputs to outputs — a clean one-way street. This one has a feedback loop, a cycle, and that single cycle is enough to change what a wire fundamentally is. Trace the loop below. Follow the output around and watch it arrive back at the input it feeds.

Watch what that loop actually does, because it's the birth of memory and it happens fast. Leave the free input — call it Set — at 0. The output sits at 0, quietly feeding 0 back to itself: stable. Now pulse Set to 1 for even an instant. The output snaps to 1. And here's the thing: that 1 now travels around the loop and lands back on the gate's own input. So the OR keeps seeing a 1 coming in, even after you let Set drop back to 0. And an OR with a 1 on any input outputs 1. It holds itself up by its own bootstraps. Pulse it and let go — the 1 stays.

So we've built the simplest memory there is — and immediately hit its fatal flaw. It's worth feeling now, because the next section's whole design exists to fix it. This latch can remember a 1, beautifully, forever. But try to put it back. Drive Set to 0 and nothing happens. The loop is still feeding itself a 1, and the OR keeps outputting 1 no matter what you do to the free input. There is no wire you can wiggle to bring it home to 0. It's a write-once memory cell with no eraser: you can set it but you can never reset it. Try every input below and watch it refuse to come down.

Now step back and notice the deep thing that just happened. It's the conceptual heart of the entire chapter, bigger than any one circuit. Look at the latch when Set is 0. What is its output? The honest answer is: I can't tell you from the inputs alone. It might be 0 (if you never pulsed it) or 1 (if you did). Same input, two possible outputs. That is a flat-out contradiction of everything determinism promised. A truth table has one row for "Set = 0" and demands one answer; this device has two. The circuit has stopped being a function of its inputs. It's now a function of its inputs plus its own history. That's the line we just crossed, and it has a name: sequential logic, logic with a past. Set the same input and watch the output disagree with itself, depending on the road you took to get there.

If a truth table can't describe this thing, then the truth table is the wrong tool. Swapping tools is how you know you've genuinely entered new territory. A truth table has no axis for "when." But this circuit's whole behaviour is about when: its output depends on the order of things that happened over time. So we reach for the instrument that has time built in — the timing diagram. It draws each wire as a horizontal track, with time running left to right. You can literally see a 1 arrive on Set, watch the output rise in response, then see it stay high long after the input has dropped away. That persistence — a line staying up with no input holding it there — is memory made visible. Read the two tracks below left to right.

02Two stable homes — the SR latch

Our OR-latch works, but it's lopsided: one-way, no eraser. To fix it we need a mental picture of what "good" memory even looks like, and physics hands us the perfect one. Picture a ball in a landscape with two valleys and a hill between them. Leave the ball in the left valley and it stays there — nudge it a little and it rolls right back. Leave it in the right valley? Same story. The system has two resting places. Each one actively holds itself, and it takes a real shove to cross from one to the other. That's called bistability, two stable states, and it is the honest shape of a memory bit. 0 is one valley, 1 is the other, and small disturbances can't tip it between them. Push the ball around below and feel the two valleys hold.

So we want two valleys. Before we wire anything, though, ask a harder question: why did the OR-latch only ever have one? The honest answer isn't our wiring. It's OR itself. An OR input can do exactly one thing to the output: a 1 on it forces the output to 1. A 0 on it forces nothing at all — it just steps aside and lets the other input decide. So there is no value you can put on any OR input that drags a 0 out of it. OR only ever pushes up. That's why the eraser was missing: not because we weren't clever enough to find it, but because with OR it cannot exist. And that hands us the shopping list. We need a gate with an input that forces the output down. Now check NOR against that list, on the table you built in Chapter 2. Put a single 1 anywhere on a NOR's inputs and the output is 0. Every time. Whatever the other input is doing. That is OR's rule held up to a mirror — OR's 1 forces high, NOR's 1 forces low. Hold that in your head, because the next five paragraphs lean on it. We didn't pick NOR. We deduced it.

Now let's build that ball-and-two-valleys out of gates. The trick is the same feedback we just discovered, done symmetrically so it works both ways. Take two of the gate we just deduced: two NOR gates. Keep both halves of its rule in your hand. A NOR is an OR with the output flipped, so it outputs 1 only when both inputs are 0 — and a single 1 anywhere on it forces the output to 0. Now cross-couple them: wire the output of the first into an input of the second, and the output of the second back into an input of the first. Each gate is now watching the other's answer. That mutual staring is the whole mechanism. The two outputs, which we'll call Q and its opposite Q̄, lock into being each other's opposite and stay that way. This is the SR latch, the canonical one-bit memory, with two control inputs left over: S (set) and R (reset). Trace the cross-coupling below.

Here's the payoff over the crippled OR-latch: this one erases. Pulse S to 1 and Q snaps to 1 and stays — set. Now pulse R to 1 and Q drops to 0 and stays — reset, the very move the OR-latch couldn't make. And when both S and R are back at 0, the latch simply holds whatever it last became. That's the full behaviour of a memory bit, in three modes: set it, reset it, or leave it alone and it remembers. Drive S and R below and store, erase, and hold a single bit with your own hands.

One thing before we open the hood, and it's the thing that makes the argument easy. Look at the latch in hold mode, with S and R both at 0. Each NOR now has one dead input — an input pinned at 0, which we just said forces nothing and steps aside. So what is a NOR with a dead input actually doing? Check it on the table you already have. NOR(0, 0) = 1, and NOR(0, 1) = 0. Feed a NOR a 0 on one input and it hands back the opposite of the other. That's an inverter. A two-input NOR with a dead input is quietly a one-input gate. Say that out loud, because it changes the picture completely: while the latch is holding, the SR latch simply is two inverters wired in a ring, each one's output feeding the other's input. Not a picture of it. The same device, with the dead inputs doing nothing. And two inverters in a ring is about the simplest object we could ever argue about.

I don't want "it just holds" to feel like hand-waving, because the why is the most beautiful part. So let's watch the loop actually settle. Say Q is currently 1 and both inputs are 0. That 1 feeds into the second NOR, whose inputs are now (1, 0). A NOR with any 1 outputs 0, so Q̄ is 0. That 0 feeds back into the first NOR, whose inputs are now (0, 0). Both low, so it outputs 1, which is Q. And that's the 1 we started with. The state proves itself: each gate's output is exactly the input the other gate needs to keep producing it. The loop isn't just sitting still. It's a tiny argument that keeps reaching the same conclusion, faster than you can perturb it. That self-reinforcement is the ball settling into its valley. Step the signal around the ring below and watch it close on itself.

Every honest engineer owes you the failure modes too, and this latch has one that textbooks love to skip past. We've used S, R, and both-low. What about both high — S = R = 1? Ask the latch to set and reset at the same instant and you get nonsense. Both NOR gates are forced to output 0, so Q and Q̄ are both 0 — no longer opposites, which was the one promise the latch made. Worse, when you release both inputs together, the loop has no defined state to fall into. It can hang for a moment, balanced on the hilltop between the valleys. That's a real, physical condition called metastability: the ball teetering on the peak before it topples one way or the other. This is the forbidden input. It's not a bug in our drawing, but a genuine hole in the naive latch that better designs have to engineer around. Drive both inputs high below and watch the contradiction.

One more question the OR-latch let us dodge, and this one can't: what does the latch read the instant you switch the power on, before anyone has touched S or R? The unsettling truth is that nobody can say. Both gates power up at once, each racing to answer before the other has. Which valley the ball tumbles into is decided by microscopic differences between the two gates: a hair more delay here, a whisper of thermal noise there. It might come up 0, it might come up 1, and it can differ from one power-on to the next. That's why real memory is garbage until initialized — the very reason your programs must set a variable before reading it. The bit is real from the first microsecond; its value is meaningless until you write one. Power-cycle the latch below and watch it land on an unpredictable state.

03Storing on command

We can now store a bit — but look at how twitchy the storing is. The SR latch reacts to S and R the moment they move. Any glitch, any stray pulse on those lines, and the stored bit changes whether you meant it or not. That's no way to run a computer, where a hundred wires are settling and rippling at once. What we really want is control over timing: a way to say "ignore your inputs entirely, except during the exact window when I tell you to listen." So we add one more wire, an enable — call it C for control. It gates whether S and R can reach the latch at all. When C is 0 the latch is sealed and holds. When C is 1 it accepts input. Toggle the enable below and watch the same inputs get through or get blocked.

The enable tames when the cell listens. But we're still carrying that hole from earlier, and it's worth going back for. Look at where the forbidden input actually lived: one row. S = R = 1. That's all of it — every other combination behaves perfectly. So here's a question worth sitting with. What if we made that row unwireable? Not guarded against. Not written up in a footnote nobody reads. Physically impossible to ask for. Look at what it would take. S and R only break the latch when they agree. So don't let them agree. Run a single wire in, send it straight to S, and send it through an inverter on its way to R. Now R is always the opposite of S, by construction — the two can never both be 1, because there's no longer a wire to say it on. The forbidden row is off the map. Now look at what that did to the controls. Drive the new wire to 1 and the cell sets, so it stores a 1. Drive it to 0 and R goes high and the cell resets, so it stores a 0. It isn't giving an order any more. It is the bit. That's not a control line, that's data — so call it D. Two commands collapsed into one value, and the flaw didn't get engineered around. It got deleted.

Now step back and read what we just built, because its behaviour has a shape you'll recognise. Forget the gates for a second and write down only what the cell does. When C is 1, Q takes the value sitting on D. When C is 0, Q keeps the value it already has. Two lines, and look at what they have in common. Each one hands you a value from one of two sources, and a control wire decides which source wins. A wire carrying a new value, a wire carrying the old value, and a line that picks which one comes out — that is a multiplexer, the 2-to-1 selector from Chapter 3, letter for letter. When the select is one way it passes input A; the other way, input B. We didn't import that. We derived the behaviour with our own hands and then found out it already had a name. Here's that MUX again so the shape is fresh in your hands. Flip its select and watch it choose between two inputs.

So the same cell can be drawn a second way, and this drawing is the cleanest memory cell in the book. Take a MUX. Wire one of its data inputs to a fresh value we'll call D (for data). Wire the other data input — the feedback input — to the MUX's own output, looped back. The select line is our enable C. Read what that does. When C = 1, the MUX passes D through, and the cell takes the new value. When C = 0, the MUX passes the other data input instead — the one wired back to its own output. So it feeds itself its current value and holds. Be careful here, because the wording traps people. With the enable low the cell does not put out a 0. It puts out whatever Q already was. That feedback path is the memory. One data wire, one enable, and the feedback we've been circling all chapter. This is the gated D latch. It has no forbidden input — not by luck, but because we deleted that row ourselves: R is wired to be the opposite of S, so the two can never both sit at 1. There's no separate set/reset dance left either, because those two commands became one value. You just present a bit and say when. Wire it below.

Let's make storing a bit into a concrete, repeatable ritual, because this exact four-beat sequence is how every register you'll ever meet writes a value. To store a bit in the gated D latch: one — put the value you want onto D. Two — raise the enable C to 1, opening the door, and the latch takes D. Three — drop C back to 0, closing the door and locking the value in. Four — now you can change D to anything you like and the stored bit doesn't budge, sealed behind the closed enable. Present, enable, latch, release. Step through the store procedure below one beat at a time.

04The catch: transparency

We have a proper one-bit memory — and now I have to show you the crack in it, because being honest about this flaw is the entire reason the next chapter exists. Go back to step two of that ritual, the moment the enable C is high. During that whole window, what is the latch doing? It isn't taking a single snapshot of D. It's passing D straight through, live, continuously. Wiggle D while C is still 1 and the output Q wiggles right along with it, tracking every change like a plain wire. The latch is transparent: you can see clean through it to D for as long as the enable is held. It only truly "remembers" the value that happened to be on D at the instant C fell. Hold the enable high below and watch the output helplessly follow its input.

Now feel why that transparency is a real problem and not a curiosity. Put it on a timing diagram, where the danger is obvious. Picture the output of our ALU wired to the D input of a latch, and imagine we hold the enable high for a stretch to "capture" the answer. But during that stretch the ALU's own output is still settling — carries rippling, bits flickering toward their final values. And because the latch is transparent, all of that churn passes straight to Q. We didn't store a value. We stored a live feed of a circuit mid-thought. The enable is high for a duration, but the thing we want to capture is a single trustworthy instant. That mismatch is the whole flaw. Watch the output smear across the transparent window below, when what we wanted was one clean sample.

And that's Chapter 7 — the chapter where a wire learned to remember. The whole climb was one idea turned over and over: a feedback loop gives a circuit a past, and a past is memory. We watched an OR gate latch itself to 1 and shatter determinism — same input, two outputs, depending on history. That is precisely the definition of sequential logic. We drew it on a timing diagram, because a truth table has no room for "when." We built the SR latch from two cross-coupled NOR gates and watched it hold a bit in either of two bistable states. We were honest about its forbidden input, its metastability, and its garbage power-on value. Then we tamed it. An enable wire and a fed-back multiplexer gave us the gated D latch — a bit you store on command with one clean ritual: present, enable, latch, release. But we end exactly where every good chapter should: on a flaw we can't paper over. The gated latch is transparent the entire time its enable is high. It echoes its input live, so it can only faithfully capture a value at the single instant the enable falls. A memory that listens for a whole window, when we need it to listen for an instant, is a memory you can't trust to hold a computer together. So the question that opens the next chapter writes itself. What if the latch could only ever change at one razor-thin moment — the edge of a signal that ticks like a metronome — and stayed frozen the rest of the time? That signal is the clock. That device is the edge-triggered flip-flop, and eight of them side by side is a register — a machine word that holds still. That's where we go next.