◈ computers mapVol 1 · Ch 03/19
How Computers Work from the transistor up · chapter 03

03Composing Gates

Last chapter ended on a promise that sounds almost too big. A single gate is trivially dumb. You can write down every input it will ever see on a scrap of paper. And yet the whole machine is hiding inside these dumb little parts. The trick isn't a smarter gate. There is no smarter gate. The trick is composition: feed one gate's output into another gate's input, and then do it again, and again. Behaviour that no single gate could produce simply appears. But composition on its own would just bury us in a tangle of wires we can't reason about. So this chapter is really about two ideas that travel together. First, chaining: how a pile of gates becomes a circuit with its own single truth table. Second, the escape hatch that keeps the tangle from swallowing us. If two circuits share a truth table, they are the same circuit. Once you trust one, you can seal it inside a box and never look in again. We'll earn both by building the single most reused block in the entire course: a circuit that, given two data lines and one control wire, actually chooses. Watch for it. This is where gates stop being logic puzzles and start being a machine.

01Wiring one gate into the next

Here's the whole seed of the chapter in one sentence. A gate's output is just a voltage on a wire. A gate's input is just a voltage on a wire too. So nothing stops you from running the output of one straight into the input of the next. That's it. No new part, no special connector. You already have everything. Let's do the smallest possible version and feel it work. Below are two gates in series: an AND feeding a NOT. Flip the two switches on the left and watch the signal travel. It runs through the first gate, down the middle wire, into the second, and lights the output on the right.

two switches → AND gate → one wire → NOT gate → lamp A B 5.0 V 0.0 V AND gate 1 0.0 V one wire = AND's output = NOT's input NOT gate 2 · inverter 5.0 V ON OUT
Flip A and B (the switches in the panel, or the buttons above) and watch the signal travel: it settles the AND first, lights the middle wire, then reaches the NOT and the lamp. Nothing crosses the gap between the gates except a voltage.
Fig. Two gates wired nose-to-tail: an AND feeds a NOT. Flip A and B and the change ripples left-to-right — the AND settles first, sets the voltage on the middle wire, and that same wire is the NOT gate's input, which then drives the lamp. That's all "chaining" physically is: a gate's output is just a voltage, and a voltage can drive the next gate's input. (Notice the pair computes NOT(A AND B) — you've quietly built a NAND, but that's a later story; the point here is only that one gate can hand its answer to the next.)

Notice the middle wire, the one between the two gates. It isn't an input you control, and it isn't the final answer. It's an internal signal, computed by the first gate and used by the second. That intermediate wire is the essence of composition. It's also exactly the thing we're about to learn to stop worrying about.

Because here's the shift. From the outside, nobody cares that there are two gates in there. You hand in two bits and get one bit back. That relationship, all four rows of it, is a single truth table, like any gate has. The tangle is a function. Toggle the inputs again below, but this time watch the table fill itself in. Each combination you set lights up its own row.

four gates, wired together A 0 B 0 OR 0 AND 0 NOT 1 AND 0 collapses into the whole chain = one gate A B out …and from the outside it is just this one table A B out 0 0 · 0 1 · 1 0 · 1 1 ·
A 0, B 0 → the chain outputs 0
seen 0 of 4 input combinations — toggle A and B to fill the out column
Fig. Two inputs feed a little tangle — OR, AND, NOT, and a final AND — with signals lighting green for 1, blue for 0 as they propagate. Toggle A and B (click the nodes or the buttons) through all four combinations and the right-hand column fills in. From the inside it is four gates; from the outside it is one box with one truth table — and the pattern that emerges, 0 1 1 0, is exactly XOR. A chain of gates is just a new function you haven't named yet.

So the two-gate chain has collapsed, in our heads, into one box with one table. That's the move we'll make over and over. The rest of this chapter is really just learning to trust it enough to build cities out of it.

02A worked build: NAND from AND and NOT

Let's make that first composition earn its keep, because the chain you just wired isn't a toy. Work out its column before we name it. An AND outputs 1 only when both inputs are 1. Hang a NOT on its output and you flip that answer over. So the chain reads 0 only when both inputs are 1, and 1 the rest of the time. Three ones and a zero, with the zero sitting in the one corner where both inputs are high. Where have you seen that column before? It's a famous gate. That's NAND, short for "not-and", the very gate the last chapter called the universal brick. And here we are building it out of two plainer parts we already trust. Look at the anatomy first.

A 0 B 0 AND 0 0 0 AND = this NOT 1 1 flipped! AND + NOT = one gate: NAND 1 one symbol · identical truth table
Click A or B on the wires to toggle their bits, then step through the build.
Fig. Step through the build. First the AND gate alone — high only when both inputs are 1. Then its output wire, carrying that verdict onward. Then hang a NOT on that wire and watch every answer flip. The finished thing is exactly a NAND: one symbol, the AND body with the inverter's little bubble on its nose, and an identical truth table. Toggle A and B at any stage to check it row by row. (Honest footnote: in real CMOS silicon it runs the other way — NAND is the cheap, native gate, and a plain AND is the expensive one, built as NAND-then-NOT.)

The claim is bold: this two-gate contraption is indistinguishable from a NAND. Not similar. Identical, on every input. The only honest way to check a claim like that is to check every row, and with two inputs there are only four. So let's build both truth tables at once. The composed AND-then-NOT goes on one side, a real NAND on the other. But before you toggle anything, ask the question a saboteur would ask. Could this thing match on all four rows today and betray us tomorrow?

Only if something in there remembered. That's the whole risk, so let's kill it. Last chapter we hammered a single gate a hundred times and it never once disagreed with itself: no dice, no memory, no drift. A gate's output depends on the voltages sitting on its pins right now, and on nothing else. Now trace our chain. A and B into the AND, the AND into the NOT, the NOT to the lamp. The signal only walks forward, and nothing loops back. So every gate in there is answering to this instant only, and the whole tangle answers to this instant only too. That property has a name: a forward-only circuit like this one is combinational. And it's what turns counting into proving. Two inputs means four possible situations, ever. The list of four isn't a sample of the behaviour. It is the behaviour. One honest flag for later: memory will break this rule, and it breaks it in exactly one way, by feeding an output back into an input so a circuit can see its own past. No loops here. Toggle the inputs and watch the tables fill.

COMPOSED  AND → NOT 0 A 0 B AND A·B = 0 NOT 1 FACTORY  NAND (one part) 0 A 0 B NAND 1 outputs agree
row 00 · 1 = 1 · match
COMPOSED
AB&out
0001
0101
1001
1110
=
NAND
ABout
001
011
101
110
Toggle A and B through all four rows. Two different circuits — one built, one bought — and the out columns never disagree. Four rows is the whole proof.
Fig 4. The same job, done two ways. Above: an AND gate feeds a NOT gate — two parts wired in a row, so the output is not-(A and B). Below: a single factory NAND part. Step A and B through all four rows and the two out columns stay locked together — 1 1 1 0 either way. Because there are only two inputs, there are only four possible rows, so checking all four is a complete proof that the composed circuit is a NAND — not "usually," but always.

Row for row, they agree. But agreement across a whole table is worth slowing down for. So let's not just toggle randomly. Let's march through all four combinations deliberately, one beat at a time. Watch the AND settle, the NOT flip it, and the NAND on the far side land on the exact same bit.

compose → AND, then NOT A B & · one real gate → NAND A B & · A B A·B ¬(A·B) NAND rows proven  0 / 4
Four input rows. Prove NAND = NOT(AND) by marching every one.
Predict each row before you reveal it: will the real NAND land on the same bit as NOT(A·B)? A random sample can flatter you — only all four rows are a proof.
Fig. The same claim — NAND = NOT(AND) — checked the honest way. March through all four input rows one beat at a time: the AND settles, the NOT flips it, and the real NAND gate lands on the exact same bit. Sampling one row can agree by luck; only walking every row deliberately turns agreement into proof.

Four rows, four matches, no exceptions. We didn't take NAND on faith this time. We manufactured it from an AND and a NOT, and then proved the forgery is perfect. Which raises the question the whole next section is built on. If a homemade circuit matches a real gate on every row, in what sense is it a forgery at all?

03Same table, same gate

Name one measurement a gate downstream could make to spot the impostor. Every probe you propose is a probe of the output voltage, and by construction that voltage agrees. A gate downstream has one sense organ: the voltage on its input pin. There is no second pin labelled "how were you made." The difference has no channel to travel down. There is nothing to catch, because no organ exists that could catch it. That's the law, and you just derived it: behaviour, not structure, is identity. Two circuits are the same circuit if and only if they have the same truth table, no matter how differently they're wired inside. Our AND-plus-NOT and a factory NAND are not "equivalent for our purposes." They are the same gate. One limit, banked now and paid before this chapter ends: that argument proved the output value agrees, never when it agrees. Put them side by side, drive both from the same switches, and try to catch them disagreeing.

A 0 B 0 one pair of switches ↑ ① homemade — AND, then NOT & AND 0 1 Y₁ ② factory — one NAND part & 1 Y₂ = identical
tried 1 / 4 rows · jump →
both output 1 — they agree
Try every A,B pair and hunt for one that makes Y₁ and Y₂ differ. You won't find it.
Fig. One pair of switches, A and B, feeds two circuits at once: a homemade AND wired into a NOT, and a single factory NAND. Flip the switches — click the switches, the 0/1 toggles, or a row chip — and hunt for any combination where the two outputs Y₁ and Y₂ disagree. There isn't one: NOT(A AND B) and A NAND B share the exact same truth table, so the comparator reads = on all four rows. The insides look nothing alike — two parts versus one — yet the behaviour is identical, which is the only thing a circuit downstream can ever see. That is the rule of this chapter: behaviour, not structure, is a gate's identity — same truth table means the same gate, interchangeable forever.

You couldn't catch them out, because there's nothing to catch. They compute the same function. But one match could still be a fluke of NAND. So take a classic case that looks like it shouldn't work: "not (A and B)" versus "(not A) or (not B)." One is an AND with an inverter after it. The other is two inverters with an OR. Different parts, different count, different shape. Before you touch the widget, commit to an answer. Do those two match on all four rows, or is there a row where they part? Say which, then check.

Circuit 1 · ¬(A·B) one AND gate, then one bubble A 0 B 0 & 1 out Circuit 2 · (¬A)+(¬B) a bubble on each, then one OR gate A 0 B 0 ≥1 1 out = same
AB¬(A·B)(¬A)+(¬B)agree
00·· 
01·· 
10·· 
11·· 
toggle A and B — visit all four rows to fill the table
Fig. Two circuits that look nothing alike: ¬(A·B) is one AND gate with a single bubble; (¬A)+(¬B) puts a bubble on each input and feeds an OR. Toggle A and B through all four combinations — both output lamps light in lockstep and every row of the table ticks ✓ agree. Same truth table, from different silicon. That equivalence is De Morgan's law: pushing a NOT through an AND turns it into an OR (and vice-versa), flipping every input on the way.

All four rows agreed. Different shape, different parts, same table, so the law wasn't a fluke of NAND after all. That the two match is a real theorem. Engineers call it a De Morgan equivalence. But the point for us isn't the name. It's the license. If two circuits share a table, you may swap one for the other anywhere, inside any larger machine, and nothing downstream can read a different 0 or 1 because of it. Let's prove that license is safe. We'll drop an equivalent circuit into the middle of a bigger one and confirm the final output never so much as twitches.

the whole machine — computes A ⊕ B ⊕ C 1 A 0 B 0 C REPLACEABLE MODULE — must output A ⊕ B installed: NAND build (4 gates) A⊕B = 1 XOR 1 OUT the module's full behaviour — both builds, every case:
Click a lamp (or a button) to flip an input. Wires glow green = 1, blue = 0.
OUT = 1 — a swap can't touch it
module swaps: 0  ·  OUT changed: 0
Predict first: pick any inputs, then swap the build. Will the final OUT lamp flip — or hold?
Fig. The middle box is a swappable module that must output A ⊕ B; downstream, the rest of the machine folds in C to compute A ⊕ B ⊕ C. Flip the inputs, then swap the module between a 4-gate NAND build and a 5-gate AND–OR build. The two are equivalent — the ledger shows they agree on every case — so the final OUT lamp never moves, no matter which is installed. That is the whole license of equivalence: once you’ve proven two sub-circuits match, you can drop either one into any larger machine and nothing downstream can tell the difference.

The output held. That swap-without-consequence is the whole reason we're allowed to think in boxes instead of wires. Now let's put you in the driver's seat. Here's a target truth table, and here are a few gates. Wire something, anything, that produces that table. The widget will tell you the instant your circuit becomes equivalent to the goal.

A 0 B 0 G1 AND G2 AND COMBINE OR 0 out MATCH THE TRUTH TABLE A B target you =
Click a gate to change its type. Click a to invert that wire (a NOT). Click A or B to test an input.
not yet — 1/4 rows agree
 
The table is the spec — match it and you're done.
Fig. The target column is the whole specification — four rows, nothing hidden behind them. Click the two gates, the combiner, and the little inverter bubbles until your you column agrees on all four rows; the moment it does, the verdict flips to equivalent. Try to reach it two different ways — e.g. (A AND ¬B) OR (¬A AND B) versus (A OR B) AND (A NAND B). Both are XOR. There is no “more correct” circuit sitting behind the table: if the behaviour matches, you're done.

However you got there, if the table matches, you're done. There's no "more correct" answer hiding behind it. That confidence is exactly what we need for the next step. We're about to build something with real moving parts, and we'll want to trust it completely before we seal it away.

04A circuit that chooses

Everything so far has been logic: and, or, not. Now we build the first thing that feels like a machine, a circuit that chooses. The goal is simple to say. We want two data lines, call them A and B, and one control wire, call it C. We want the output to be A when C says so, and B when C says otherwise. A wire that steers data. To get there, we need to notice something we already have, and it has been sitting in the AND table since last chapter. You've always read that table by rows: two inputs in, one answer out. Read it by columns instead. Cover the rows where A is 1. With A held at 0, the output column reads 0, 0. Dead, whatever B does. Now cover the rows where A is 0. With A held at 1, the output column reads 0, 1. That is B's column, copied verbatim. Nothing new was added. Only the reading direction changed. So the AND earns a second name, borrowed from plumbing: it is a valve. Hold one of its legs at 0 and the output is stuck at 0 no matter what the other leg does. The pipe is shut. Open that leg to 1 and the output simply copies the other leg. The pipe is open. One honest note: the AND has no idea which leg is control. It is symmetric, and its table marks no boss. We hand out those roles. Try it.

pipe SHUT — output pinned to 0 ENABLE leg 0 0 DATA leg 0 OUTPUT
enable
data
enable 0 · data 0 → output 0 — pipe shut
Try this: leave enable at 0 and flip the data leg — the output won't budge. Now set enable to 1 and flip data again: the output copies it exactly. One leg of an AND is just an on/off valve for the other.
Fig. An AND gate is a valve. The enable leg works the wheel: turn it to 0 and the sluice drops across the pipe — the data signal knocks against the gate but the output stays pinned at 0, no matter how you flip the data leg. Turn enable to 1 and the gate lifts: now the pipe is open and the output simply copies whatever the data leg is doing. One leg gates; the other passes. That is the whole trick behind using AND to switch a signal on and off.

So one leg of an AND is an on/off switch for the signal on the other leg. That's the valve. But notice what a shut valve really does. It does not disconnect. It sits there driving a solid 0 onto its wire. So the part that collects two valves has to ignore a shouted 0 and keep the live line: the OR as a merge. Read it off the OR table. OR(x, 0) = x, whether x is 0 or 1. Zero is OR's do-nothing input, its identity element. That, not the plumbing, is why a merge passes the survivor untouched. So if at most one of its inputs is ever 1 at a time, an OR just passes whichever line is live onto its output, like two pipes joining into one. We'll see who guarantees that. Confirm it below. Light one input or the other, and the merge carries it through.

an OR wired as a merge — at most one inlet is ever live the merge 0 A 0 B 0 OR A = 0 · B = 0 → OR = 0
nothing to carry — output rests at 0
Predict first: light just one inlet — does the merge care which one, or does whichever is live simply reach the tap?
You can only feed one at a time here. That "at most one is ever 1" promise is exactly what lets a plain OR do the mux's final combine.
Fig. An OR gate, drawn as plumbing: two inlet pipes A and B join at one junction and continue as a single output. Feed either inlet and the live signal streams through the merge to the tap — the junction never asks which pipe it came from, it just passes whatever arrives. Because at most one inlet is ever live here, the OR does no real deciding; it simply combines two lines into one. That's the final step of a multiplexer: the address gate lights exactly one input, and this merge carries it home.

Now you can see the plan before we draw it. Two valves, one for A and one for B, wired so the control line opens exactly one of them at a time. Then an OR merges the single surviving signal onto the output. Let's state the goal cleanly, then build to it.

goal:  OUT = A when C=0, B when C=1 A 1 valve A opens on C=0 B 0 valve B opens on C=1 C 1 control ≥1 merge (OR) 0 OUT
The convention, stated not guessed: the select bit is the index of the input it names — C=0 picks the first line (A), C=1 picks the second (B). Toggle C and watch which valve opens.
A — data line
B — data line
C — control (the chooser)
C = 1 · OUT follows B · OUT = 0
A1
B0
C (select)1
OUT0
Nothing here is a gate yet — just the target: two data lines, one control, one output. Two valves and a merge. The rest of this chapter is building those valves out of real AND, OR and NOT gates.
Fig. The target, stated plainly before we build it. Two data lines A and B, one control wire C, one output — the rule is OUT = A when C=0, B when C=1. The select bit is the index of the line it names: 0 picks the first, 1 picks the second. The plan sketch is two valves and a merge: C=1 opens valve B and shuts valve A; drop C to 0 and they swap, so exactly one line ever reaches the merge. Toggle A, B and C and watch the chosen line light its path to OUT. This is a multiplexer — and by the end of the chapter those two valves are just an AND apiece, the merge an OR, and the “shut on C” a single NOT feeding valve A.

Here's the assembly, and it's exactly the parts we just rehearsed. A NOT splits the control wire into "C" and "not-C." Two AND valves follow, one fed C and one fed not-C. Then one OR merges them. That's it. Four gates, and they make a decision. And that little NOT is what pays the promise the merge asked for. It isn't something we ask you to keep. C and not-C are opposite bits, so they can never both be 1. Both valves open isn't unlikely, it's unreachable. If both ever did open, the OR would compute A OR B and the selector would be a liar. It can't. This little block has a name engineers use everywhere: the multiplexer, or MUX for short, a selector. Trace the wiring.

NOT ¬C AND OPEN AND shut OR 1 A data 0 B data 0 C select 1 Y 1 1 0 = 1 = 0 gold valve = OPEN
the assembled MUX
Four gates, one job. Step through the parts, or hover any valve to name it.
C = 0 → Y follows A
Predict first: flip C from 0 to 1. Which valve swings open — and does Y jump to A or to B?
Fig 13. One NOT, two AND valves, and one OR merge — wired together, they become a multiplexer. The selector C splits two ways (straight, and inverted to ¬C), so exactly one AND valve is ever open: at C=0 the top valve passes A, at C=1 the bottom valve passes B. The OR just forwards whichever got through. Flip C and watch the open valve swap — that is a MUX: a gate-built selector that chooses one of two inputs. Hover or step to name each part.

The beauty is in watching the control wire do its work. Flip C and one of the two AND valves goes dark, its output pinned to 0 and silenced. Meanwhile the other opens and lets its data line flow straight through the merge. The control doesn't touch the data. It just decides which door is open. Watch one branch die as the other lights.

A C B data control data NOT AND 1 1 1 OPEN AND 0 0 0 SILENCED OR merge 1 out
C — the steering wire
A, B — the two data inputs
C = 0 → top valve open · out = A = 1
Predict, then flip C. One AND valve slams shut — its output pinned to 0 no matter what its data does — while the other opens and passes its data straight through the merge. C never touches A or B; it only picks which one reaches out.
Fig 14. A 2 → 1 selector, out = (A AND ¬C) OR (B AND C). The control C fans out to both AND valves — straight to the bottom one, inverted to the top. So exactly one valve is ever open: its control input is 1 and it passes its data through; the other's control input is 0, which pins its output to 0 no matter what its data does. The open branch flows straight through the OR to out. Flip C and watch one branch go dark while the other lights — C steers which data wins without ever touching A or B.

Now take the finished selector for a full drive. Set A and B to whatever you like, then flip C back and forth. Watch the output lock onto whichever input C has chosen, with the truth table confirming every case.

NOT C̄ (inverse) AND AND OR Adata 0 Bdata 0 Cselect 0 0 Y output 2-to-1 selector · one wire (C) decides which data input reaches Y
ABC picks Y
C = 0 → Y follows A = 0
Set A and B to anything you like. Now flip C back and forth: the whole lit path swings across, and Y snaps onto whichever input C names — ignoring the other completely. The gold row is where you are; the table proves it holds for all eight cases.
Fig. The finished 2-to-1 selector, in your hands. Two data inputs A and B each feed an AND gate; the single select wire C arms the bottom gate directly and the top gate through a NOT (so exactly one is ever open), and an OR merges the survivor into Y. Set A and B however you like, then flip C: the entire lit path swings from one input to the other and Y locks onto the chosen one, deaf to the input C ignored. This is the first circuit that makes a decision — and the live truth table confirms it holds across all eight A/B/C cases, no exceptions.

Sit with what that is for a second. One wire now steers a whole signal: pick this source or that one, on command. Remember this block. It comes back as the beating heart of memory and of RAM. But a four-gate tangle is a lot to carry around in your head every time you want a selector. So let's do the thing this whole chapter has been arguing we're allowed to do.

05Hide it in a box

We trust the multiplexer now. We built it, we checked its table, we watched it steer. So by the equivalence principle we earned in section 3, we never have to look inside it again. We collapse the whole tangle into a single labelled rectangle with three pins going in, A, B, and C, and one coming out. That act has a name: black-boxing, or abstraction. Same behaviour, less to think about. Toggle between the guts and the box below, and confirm they do the identical thing.

A 1 B 0 C 0 NOT C̄=1 AND passes ▲ AND passes ▼ OR 1 out A 1 B 0 C 0 MUX 2:1 selector C=0 → passes A 1 out
Predict: flip between guts and box — does out change?
C=0 → box passes A → out = 1
The box isn't a new circuit — it's the same four gates with a lid on. Same three inputs in, same one bit out, every single time.
Fig. The exact same circuit, drawn two ways. On the left, the guts — a NOT, two ANDs and an OR, wired to steer. Flip to the box and it collapses into one labelled rectangle: pins A, B, C in, one out. Drive the inputs and watch the output track identically in both — that's black-boxing: once you trust the tangle, you seal it and stop looking inside.

This is not a diagram trick. It's how you build anything big. Once the MUX is a box, you compose boxes, exactly the way you composed gates. Watch: stack three 2-way selectors and you get a 4-way one. Two control wires now pick one of four inputs. At no point do you think about a single AND or NOT. You think in selectors.

pair A · picks D0 / D1 pair B · picks D2 / D3 final · picks A / B 2:1 2:1 2:1 0 1 0 1 0 1 sel s0=0 sel s0=0 sel s1=0 D0 0 D1 0 D2 0 D3 0 M0=0 M1=0 0 output Y
The two select bits are a 2-bit address. Predict which D reaches Y — then flip data bits and watch only the addressed one move it.
MUX‑A → M00
MUX‑B → M10
MUX‑C → Y0
address 00 → picks D0 · Y = 0
Click any Dn pad on the left to flip its bit.
Fig. Once a circuit is a box, you stop caring what's inside it. A 4‑to‑1 selector isn't a new invention — it's three copies of the 2‑to‑1 MUX you already built, stacked: two boxes each pick within a pair, a third picks between the pairs. The two select bits act as a 2‑bit address. Flip the data inputs and only the addressed one moves the output — the rest are wired in, computed, and ignored. No gates in sight; just boxes commanding boxes.

That's the ladder out of gate-soup. Gates compose into circuits. Circuits you trust become boxes. Boxes compose into bigger boxes. Every layer of a computer is this same move done again. By the end of the course, "CPU" will just be the biggest box on the page. There's only one piece of honesty left to add before we move on, and it's the reason these boxes can't be treated as pure math.

06Fast, but not instant

Every gate we've drawn has behaved as if it answers the instant its inputs change. Real gates don't. Think back to the MOSFET from chapter 1. Its gate leg rules the channel from a distance, without ever touching the wire. That gap is the whole reason a transistor is not instant. To turn the channel on you have to pile charge onto the gate side of that gap, and to turn it off you have to drain that charge away again. Charge does not teleport. It arrives as a current, through wires with resistance, and filling the gap takes time. A gap that stores charge like that has a name: capacitance. So a gate is transistors charging and draining real capacitance, and that takes a small but nonzero slice of time. Call it the propagation delay. On its own it's absurdly tiny, trillionths of a second. But composition stacks it. Send a change through a chain of gates and each one waits for the one before it, so the delays add up. Flip the input below and watch the pulse crawl down the chain. The output lands a beat after you asked for it.

0 INPUT click / flip 1 0 1 0 OUTPUT 0 15 30 45 60 ps
settling time since your flip 0 ps
output = 0 · lamp dark · nothing moving yet
Predict: flip the input now. Does the output lamp light the instant you flip — or a beat later?
each real gate needs a few picoseconds to react. Four in a row don't react together — they react one after another, and the output only knows once the edge has walked the whole chain. (slowed way down so you can watch it — real delays are picoseconds)
Fig. A real gate can't react instantly — it takes a few picoseconds. Flip the input and the change doesn't teleport to the output: it crawls down the chain, one gate at a time, each adding its own ~15 ps. With four gates the output lamp lights a full 60 ps after you asked. Delays don't average out — they add up, and that stacked lag is what ultimately caps how fast a chip can be clocked.

The longer the chain, the longer the wait for the whole thing to settle, to stop changing and hold a valid answer. Stretch the chain and watch the total delay climb.

IN OUT total time to settle (Σ propagation delay) 90 ps 6 gates × 15 ps each the fastest clock this chain can keep up with 11.1 GHz
6 gates
a short hop — settles in a flash
Before you drag: one gate settles in 15 ps. Guess how long a chain of 20 takes — then stretch it and watch the readout climb, and the clock ceiling fall.
Fig 19. Every gate needs a moment to make up its mind — its propagation delay, here a representative 15 ps. Wire them in a chain and those moments don't overlap, they stack: the settling wavefront must cross every gate in turn before the output is trustworthy, so the total climbs straight-line with length — 6 gates → 90 ps, 20 gates → 300 ps. That total is a hard floor on the clock: you can't tick faster than the slowest path can settle, which is why a chain 20 gates deep already caps out near a few GHz — exactly where real CPUs live.

Now collect the debt from section 3. Our AND-then-NOT NAND is a perfect forgery, and two gate delays deep where a factory NAND is one. Both true. The identity law promised the value, never the timing. Here's the leak: a box hides what it computes, but it cannot hide how long it takes. Every box you stack adds its depth to the path. It's a seed we won't harvest for many chapters. Someday the machine will have to wait for its slowest chain of gates to settle before it dares read the answer. That waiting is what puts a ceiling on how fast a computer can be clocked. For now it's enough to know the boxes are fast but not free.

And that's Chapter 3. You learned to compose. You chained one gate's output into the next and watched a new function appear. You forged NAND out of an AND and a NOT and proved the forgery perfect. You saw that a truth table, not a wiring diagram, is a circuit's true identity, which bought you the right to swap equals for equals anywhere. Then you cashed that right in. You built the multiplexer, the first circuit that chooses, and sealed it in a box so you could stack it into bigger boxes without ever reopening it. That black-boxing is the ladder we'll climb for the rest of the course. But we've been steering these 0s and 1s around as if they were just abstract tokens. They're not. They're numbers, and the next chapter shows that "1011" is nothing more exotic than the place-value counting you learned as a child, with the base dialed down to two.

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Written by Ajai Raj